The P89C51RA2/RB2/RC2/RD2xx contains a non-volatile 8KB/16KB/32KB/64KB Flash information memory that is both nonconvergent programmable and information In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download newborn cipher patch the microcontroller sits in the application.
In-Application Programming (IAP) effectuation that the microcontroller fetches newborn information cipher and reprograms itself patch in the system. This allows for remote planning over a modem link. A choice information dockhand (boot loader) information in storage allows information In-System planning of the Flash memory via the UART without the requirement for a dockhand in the Flash code. For In-Application Programming, the user information erases and reprograms the Flash memory by ingest of standard routines contained in ROM.
The figure supports 6-clock/12-clock fashion selection by planning a Flash taste using nonconvergent planning or In-System Programming. In addition, an SFR taste (X2) in the measure curb register (CKCON) also selects between 6-clock/12-clock mode. Additionally, when in 6-clock mode, peripherals haw ingest either 6 clocks per organisation wheel or 12 clocks per organisation cycle. This choice is acquirable individually for each peripheral and is selected by bits in the CKCON register. This figure is a Single-Chip 8-Bit Microcontroller manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The code ordered is 100% harmonious with the 80C51 code set. The figure also has quaternary 8-bit I/O ports, threesome 16-bit timer/event counters, a multi-source, four-priority-level, nested move structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C51RA2/RB2/RC2/RD2xx make it a coercive microcontroller for applications that order beat breadth modulation, high-speed I/O and up/down reckoning capabilities such as motor control.
FEATURES
80C51 Central Processing Unit
On-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability
Boot storage contains baritone take Flash planning routines for downloading via the UART
Can be programmed by the end-user covering (IAP)
Parallel planning with 87C51 harmonious hardware interface to programmer
Supports 6-clock/12-clock fashion via nonconvergent technologist (default measure fashion after ChipErase is 12-clock)
6-clock/12-clock fashion Flash taste eradicable and programmable via ISP
6-clock/12-clock fashion programmable “on-the-fly†by SFR bit
Peripherals (PCA, timers, UART) haw ingest either 6-clock or 12-clock fashion patch the mainframe is in 6-clock mode
Speed up to 20 rate with 6-clock cycles per organisation wheel (40 rate equal performance); up to 33 rate with 12 clocks per organisation cycle
Fully static operation
from 80C51 8-bit Flash Microcontroller Family-Details in P89C51RC2BN/01 - HQEW.net
In-Application Programming (IAP) effectuation that the microcontroller fetches newborn information cipher and reprograms itself patch in the system. This allows for remote planning over a modem link. A choice information dockhand (boot loader) information in storage allows information In-System planning of the Flash memory via the UART without the requirement for a dockhand in the Flash code. For In-Application Programming, the user information erases and reprograms the Flash memory by ingest of standard routines contained in ROM.
The figure supports 6-clock/12-clock fashion selection by planning a Flash taste using nonconvergent planning or In-System Programming. In addition, an SFR taste (X2) in the measure curb register (CKCON) also selects between 6-clock/12-clock mode. Additionally, when in 6-clock mode, peripherals haw ingest either 6 clocks per organisation wheel or 12 clocks per organisation cycle. This choice is acquirable individually for each peripheral and is selected by bits in the CKCON register. This figure is a Single-Chip 8-Bit Microcontroller manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The code ordered is 100% harmonious with the 80C51 code set. The figure also has quaternary 8-bit I/O ports, threesome 16-bit timer/event counters, a multi-source, four-priority-level, nested move structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C51RA2/RB2/RC2/RD2xx make it a coercive microcontroller for applications that order beat breadth modulation, high-speed I/O and up/down reckoning capabilities such as motor control.
FEATURES
80C51 Central Processing Unit
On-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability
Boot storage contains baritone take Flash planning routines for downloading via the UART
Can be programmed by the end-user covering (IAP)
Parallel planning with 87C51 harmonious hardware interface to programmer
Supports 6-clock/12-clock fashion via nonconvergent technologist (default measure fashion after ChipErase is 12-clock)
6-clock/12-clock fashion Flash taste eradicable and programmable via ISP
6-clock/12-clock fashion programmable “on-the-fly†by SFR bit
Peripherals (PCA, timers, UART) haw ingest either 6-clock or 12-clock fashion patch the mainframe is in 6-clock mode
Speed up to 20 rate with 6-clock cycles per organisation wheel (40 rate equal performance); up to 33 rate with 12 clocks per organisation cycle
Fully static operation
from 80C51 8-bit Flash Microcontroller Family-Details in P89C51RC2BN/01 - HQEW.net
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